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syncmos 1 f 29c51001t/ f 29c51001b 1 megabit (131,072 x 8 bit) 5 v olt cmos flash memor y f 29c51001t/ f 29c51001b v1.0 m a y 1999 features n 128kx8-bit organization n address access time: 45, 70, 90 ns n single 5v 10% power supply n sector erase mode operation n 8kb boot block (lockable) n 512 bytes per sector, 256 sectors sector-erase cycle time: 10ms (max) byte-program cycle time: 20 m s (max) n minimum 10,000 erase-program cycles n low power dissipation active read current: 20ma (typ) active program current: 30ma (typ) standby current: 100 m a (max) n hardware data protection n low v cc program inhibit below 3.2v n self-timed program/erase operations with end- of-cycle detection data polling toggle bit n cmos and ttl interface n available in two versions ? f 29c51001t (top boot block) ? f 29c51001b (bottom boot block) n packages: 32-pin plastic dip 32-pin tsop-i 32-pin plcc description the f 29c51001t/ f 29c51001b is a high speed 131,072 x 8 bit cmos flash memory. programming or erasing the device is done with a single 5 volt power supply. the device has separate chip enable ce, program enabl e we , and output enable oe controls to eliminate bus contention. the f 29c51001t/ f 29c51001b offers a combi- nation of features: boot block with sector erase mode. the end of program/erase cycle is detected by data polling of i/o 7 or by the toggle bit i/o 6 . th e f 29c51001t/ f 29c51001b features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. the device also supports full chip erase. boot block architecture enables the device to boot from a protected sector loaded either at the top ( f 29c51001t) or the bottom ( f 29c51001b) sector. all inputs and outputs are cmos and ttl compatible. th e f 29c51001t/ f 29c51001b is ideal for applications that require updatable code and data storage. device usage chart operating temperature range package outline access time (ns) power temperature mar k p t j 4 5 7 0 9 0 std. 0 c to 70 c blank ?0 c to +85 c i
2 syncmos f 29c51001t/ f 29c51001b f 29c51001t/ f 29c51001b v1.0 m a y 1999 operating voltage 51: 5v 31: 3v device speed 51001-01 v 29 c 001 51 boot block location t: top b: bottom t 45: 45ns 70: 70ns 90: 90ns blank (standard) blan k (0 c to 70 c) ind (-40 c to +85 c) p = pdip t = tsop-i j = plcc power temp. pkg. pin configurations n/c a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 30 31 32 29 28 27 26 25 7 24 23 22 21 20 32-pin pdip top view v cc we nc a14 a13 a8 a9 a11 oe a10 ce i/o3 i/o4 i/o5 i/o6 i/o7 19 18 17 51001-02 pin names a 0 ? 16 address inputs i/o 0 ?/o 7 data input/output ce chip enable oe output enable we program enable v cc 5v 10% power supply gnd ground n c no connect a11 a9 a8 a13 a14 nc we v cc n/c a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 30 31 32 29 28 27 26 25 7 24 23 22 21 20 32-pin tsop i standard pinout top view oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 a3 a2 a1 a0 i/o0 19 18 17 51001-04 a 6 a 5 a 4 a 3 a 2 a 1 i/o 0 5 6 7 8 9 10 11 12 13 29 51001-03 28 27 26 25 24 23 22 21 a 12 a 15 a 16 nc v cc we nc a 0 14 i/o 2 gnd i/o 3 i/o 4 i/o 5 i/o 6 a 7 a 13 a 8 a 9 a 11 oe a 10 i/o 7 ce a 14 i/o 1 32 pin plcc top view 1 5 1 6 1 7 1 8 1 9 20 4 3 2 1 3 2 3 1 30
syncmos F29C51001t/F29C51001b 3 F29C51001t/F29C51001b v1.0 may 1999 functional block diagram capacitance (1,2) note: 1. capacitance is sampled and not 100% tested. 2. t a = 25 c, v cc = 5v 10%, f = 1 mhz. latch up characteristics (1) note: 1. includes all pins except v cc . test conditions: v cc = 5v, one pin at a time. ac test load symbol parameter test msetup typ. max. units c in input capacitance v in = 0 6 8 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v in = 0 8 10 pf paramete r min. max. unit input voltage with respect to gnd on a 9 , oe -1 +13 v input voltage with respect to gnd on i/o, address or control pins -1 v cc + 1 v v cc current -100 +100 ma address buffer & latche s a 0 ea 16 51001-05 i/o buffer & data latches i/o 0 ei/o 7 y-decoder 1,048,576 bit memory cell array x-decoder control logic ce oe we 51001-06 in3064 or equivalent in3064 or equivalent 2.7 k ? 6.2 k ? +5.0 v in3064 or equivalent in3064 or equivalent c l = 100 pf device under test
4 syncmos F29C51001t/F29C51001b F29C51001t/F29C51001b v1.0 may 1999 absolute maximum ratings (1) note: 1. stress greater than those listed unders absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational s e ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. no more than one output maybe shorted at a time and not exceeding one second long. dc electrical characteristics (over the commercial operating range) symbol parameter commercial extended unit v in input voltage (input or i/o pins) -2 to +7 -2 to +7 v v in input voltage (a 9 pin, oe ) -2 to +13 -2 to +13 v v cc power supply voltage -0.5 to +5.5 -0.5 to +5.5 v t stg storage temerpature (plastic) -65 to +125 -65 to +150 c t opr operating temperature 0 to +70 -40 to + 125 c i out short circuit current (2) 200 (max.) 200 (max.) ma parameter name parameter test conditions min. max. unit v il input low voltage v cc = v cc min. ? 0.8 v v ih input high voltage v cc = v cc max. 2 ? v i il input leakage current v in = gnd to v cc , v cc = v cc max. ? 1 m a i ol output leakage current v out = gnd to v cc , v cc = v cc max. ? 1 m a v ol output low voltage v cc = v cc min., i ol = 2.1ma ? 0.4 v v oh output high voltage v cc = v cc min, i oh = -400 m a 2.4 ? v i cc1 read current ce = oe = v il , we = v ih , all i/os open, address input = v il /v ih , at f = 1/t rc min., v cc = v cc max. ? 40 ma i cc2 program current ce = we = vil, oe = v ih , v cc = v cc max. ? 50 ma i sb ttl standby current ce = oe = we = v ih , v cc = v cc max. ? 2 ma i sb1 cmos standby current ce = oe = we = v cc e 0.3v, v cc = v cc max. ? 100 m a v h device id voltage for a 9 ce = oe = v il , we = v ih 11.5 12.5 v i h device id current for a 9 ce = oe = v il , we = v ih , a9 = v h max. ? 50 m a
s yn c mos F29C51001t/F29C51001b 5 F29C51001t/F29C51001b v1.0 may 1999 ac electrical characteristics (over all temperature ranges) read cycle program (erase/program) cycle parameter name parameter -45 -70 -90 uni t min. max. min. max. min. max. t rc read cycle time 45 ? 70 ? 90 ? ns t aa address access time ? 45 ? 70 ? 90 ns t acs chip enable access time ? 45 ? 70 ? 90 ns t oe output enable access time ? 25 ? 35 ? 45 ns t clz ce low to output active 0 ? 0 ? 0 ? ns t olz oe low to output active 0 ? 0 ? 0 ? ns t df output enable or chip disable to output in high z 0 15 0 20 0 30 ns t oh output hold from address change 0 ? 0 ? 0 ? ns parameter name parameter -45 -70 -90 uni t min . typ . max . min . typ . max . min . typ . max. t wc program cycle time 45 ? ? 70 ? ? 90 ? ? ns t as address setup time 0 ? ? 0 ? ? 0 ? ? ns t ah address hold time 35 ? ? 45 ? ? 45 ? ? ns t cs ce setup time 0 ? ? 0 ? ? 0 ? ? ns t ch ce hold time 0 ? ? 0 ? ? 0 ? ? ns t oes oe setup time 0 ? ? 0 ? ? 0 ? ? ns t oeh oe high hold time 0 ? ? 0 ? ? 0 ? ? ns t wp we pulse width 25 ? ? 35 ? ? 45 ? ? ns t wph we pulse width high 20 ? ? 35 ? ? 38 ? ? ns t ds data setup time 20 ? ? 25 ? ? 30 ? ? ns t dh data hold time 0 ? ? 0 ? ? 0 ? ? ns t whwh1 programming cycle ? ? 20 ? ? 20 ? ? 20 m s t whwh2 sector erase cycle ? ? 10 ? ? 10 ? ? 10 ms t whwh3 chip erase cycle ? 500 ? ? 500 ? ? 500 ? ms
6 syncmos F29C51001t/F29C51001b F29C51001t/f 29c51001b v1.0 may 1999 waveforms of read cycle waveforms of we controlled-program cycle notes: 1. i/o 7 : the output is the complement of the data written to the device. 2. pa: the address of the memory location to be programmed. 3. pd: the data at the byte address to be programmed. t rc t aa t ce t oe t clz t oh t aa t olz t df address ce oe we i/o valid data out valid data out high-z 51001-07 high-z t wc t as p a 5555h t whwh1 t wph t cs t rc t ah t ds t dh t wp t oes t df t oh t oe d ou t i/o 7 (1) pd (3) a0h 51001-08 address ce oe we i/o 3rd bus cycle pa (2) t ch
syncmos F29C51001t/F29C51001b 7 F29C51001t/f 29c51001b v1.0 may 1999 waveforms of ce controlled-program cycle waveforms of erase cycle (1) notes: 1. pa: the address of the memory location to be programmed. 2. pd: the data at the byte address to be programmed. 3. sa: the sector address for sector erase. address = don?t care for chip erase. t wc t as t whwh1 t wph t oes t rc t ah t ds t dh t wp t df t oh t oe d ou t i/o 7 pd (2) a0h 51001-09 address 5555h pa pa (1) we oe ce i/o t wc t as t wph address ce oe we i/o 5555h 5555h 5555 h 2aaah 2aaah sa aah 55h 80h aah 55h 30h 10h for chip erase 51001-10 t ah t wp t ds t dh t cs
8 syncmos F29C51001t/F29C51001b F29C51001t/f 29c51001b v1.0 may 1999 waveforms of data polling cycle waveforms of toggle bit cycle t oeh t ce t whwh1 t oh t df t ch ce oe we i/o 7 i/o 7 i/o 7 valid data out high-z t oe 51001-11 i/o 0 -i/o 6 i/o 0 -i/o 6 invalid valid data out high-z 51001-12 ce we oe t oeh i/o 6
9 F29C51001t/f 29c51001b v1.0 may 1999 syncmos F29C51001t/F29C51001b functional description th e F29C51001t/F29C51001b consists of 256 equally-sized sectors of 512 bytes each. the 8 kb lockable boot block is intended for storage of the system bios boot code. the boot code is the first piece of code executed each time the system is powered on or rebooted. the F29C51001 is available in two versions: the F29C51001t with the boot block address starting from 1e000h to 1ffffh, and the F29C51001b with the boot block address starting from 00000h to 1ffffh. read cycle a read cycle is performed by holding bot h ce an d oe signals low. data out becomes valid only when these conditions are met. during a read cycle we must be high prior to ce and oe going low. we must remain high during the read operation for the read to complete (see table 1). output disable returnin g oe or ce high, whichever occurs first will terminate the read operation and place the l/o pins in the high-z state. standby the device will enter standby mode when the ce signal is high. the l/o pins are placed in the high-z, independent of the oe signal. byte program cycle th e F29C51001t/F29C51001b is programmed on a byte-by-byte basis. the byte program operation is initiated by using a specific four-bus- cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see table 2). during the byte program cycle, addresses are latched on the falling edge of eithe r ce or we , whichever is last. data is latched on the rising edge o f ce or we , whichever is first. the byte program cycle can be ce controlled or we controlled. sector erase cycle the F29C51001t/F29C51001b features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. sector erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see table 2). a sector must be first erased before it can be reprogrammed. while in the internal erase mode, the device ignores any program attempt into the device. the internal erase completion can be determined via data polling or toggle bit. th e F29C51001t/F29C51001b is shipped with pre-erased sectors (all bits = 1). 8kb boot block 512 512 512 512 512 512 512 512 8kb boot block F29C51001t F29C51001b 1ffffh 1e000h 00000h 01fffh 51001-13 00000h 8kb boot block = 16 sectors table 1. operation modes decoding decoding mode ce oe we a 0 a 1 a 9 i/o read v il v il v ih a 0 a 1 a 9 read byte write v il v ih v il a 0 a 1 a 9 pd standby v ih x x x x x high-z autoselect device id v il v il v ih v ih v il v h code autoselect manufacture id v il v il v ih v il v il v h code enabling boot block protection lock v il v h v il x x v h x
10 syncmos F29C51001t/F29C51001b F29C51001t/f 29c51001b v1.0 may 1999 notes: 1. x = don? care, v ih = high, v il = low. v h = 12.5v max. 2. pd: the data at the byte address to be programmed. table 2. command codes notes: 1. top boot sector 2. bottom boot sector 3. pa: the address of the memory location to be programmed. 4. pd: the data at the byte address to be programmed. disabling boot block protection lock v h v h v il x x v h x output disable v il v ih v ih x x x high-z command sequence first bus program cycle second bus program cycle third bus program cycle fourth bus program cycle fifth bus program cycle six bus program cycle address data address data address data address data address data address data read xxxxh f0h read 5555h aah 2aaah 55h 5555h f0h ra rd autoselect 5555h aah 2aaah 55h 5555h 90h 00h 40h 01h 01h (1) a1h (2) byte program 5555h aah 2aaah 55h 5555h a0h pa pd(4) chip erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector eras e 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h pa(3) 30h decoding mode ce oe we a 0 a 1 a 9 i/o chip erase cycle th e F29C51001t/F29C51001b features a chip- erase operation. the chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see table 2). the chip erase operation is performed sequentially, one sector at a time. when the automated on chip erase algorithm is requested with the chip erase command sequence, the device automatically programs and verifies the entire memory array for an all zero pattern prior to erasure the automatic erase begins on the rising edge of the last we or ce pulse in the command sequence and terminates when the data on dq7 is ?? program cycle status detection there are two methods for determining the state of th e F29C51001t/F29C51001b during a program (erase/program) cycle : data polling (i/o 7 ) and toggle bit (i/o 6 ). data polling (i/o 7 ) th e F29C51001t/F29C51001b features data polling to indicate the end of a program cycle. when the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on i/o 7 . once the program cycle is completed, i/o 7 will show true data, and the device is then ready for the next cycle. toggle bit (i/o 6 ) th e F29C51001t/F29C51001b also features another method for determining the end of a program cycle. when the device is in the program cycle, any attempt to read the device will result in l/o 6 toggling between 1 and 0. once the program is completed, the toggling will stop. the device is then ready for the next operation. examining the toggle bit may begin at any time during a program cycle.
11 F29C51001t/f 29c51001b v1.0 may 1999 syncmos F29C51001t/F29C51001b boot block protection the F29C51001t/F29C51001b features hardware boot block protection. the boot block sector protection is enabled when high voltage (12.5v) is applied to oe and a9 pins with ce pin low an d we pin low. the sector protection is desabled when high voltage is applied to oe , ce and a9 pins with we pin low. other pins can be high or low. this is shown in table 1. autoselect th e F29C51001t/F29C51001b features an autoselect mode to identify the boot block (protected/unprotected), the device (top/bottom), and the manufacturer id. to get to the autoselect mode, a high voltage (v h ) must be applied to the a 9 pin. once the a 9 signal is returned to low or high, the device will return to the previous mode. boot block protection status in autoselect mode, performing a read at address 3cxx2h or address 0cxx2h will indicate if the top boot block sector or the bottom boot block sector is locked out. if the data is 01h, the top/bottom boot block is protected. if the data is 00h, the top/bottom boot block is unprotected. (see table 3.) device id in autoselect mode, performing a read at address xxxxh will determine whether the device is a top boot block device or a bottom boot block device. if the data is 01h, the device is a top boot block. if the data is a1h, the device is a bottom boot block device (see table 3). in addition, the device id can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the a 9 pin. when a 0 is high, the device id is presented at the outputs. manufacturer id in autoselect mode, performing a read at address. xxxx0h will determine the manufacturer id. 40h is the manufacturer code for syncmos flash. in addition the manufacturer id can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the a 9 pin. when a 0 is low, the manufacturer id is presented at the outputs. hardware data protection v cc sense protection: the program operation is inhibited when vcc is less than 2.5v. noise protection: a ce or we pulse of less than 5ns will not initiate a program cycle. program inhibit protection : holding any one of oe low, ce high or we high inhibits a program cycle. table 3. autoselect decoding note: 1. x = don?t care, v ih = high, v il = low. decoding mode boot block address data i/o 0 ei/o 7 a 0 a 1 a 2 ea 13 a 14 ea 16 boot block protection top v il v ih x v ih 01h: protected bottom v il v ih x v il 00h: unprotected device id top v ih v il x x 01h bottom a1h manufacture id v il v il x x 40h
12 syncmos F29C51001t/F29C51001b F29C51001t/f 29c51001b v1.0 may 1999 byte program algorithm chip/sector erase algorithm write program command sequence add/data 5555h/aah 2aaah/55h 5555h/a0h four bus cycle sequence pa/pd data polling (i/o7) or toggle bit (i/o6) programming completed verify byte? yes no write erase command sequence add/data 5555h/aah 2aaah/55h 5555h/80h six bus cycle sequence 5555h/aah 2aaah/55h 5555h/10h (chip erase) pa/30h (sector erase data polling or toggle bit successfully completed erase complete 51001-14
syncmos F29C51001t/F29C51001b 13 F29C51001t/f 29c51001b v1.0 may 1999 data polling algorithm toggle bit algorithm note: 1. pba: the byte address to be programmed. read i/o 7 address = pba (1) program done program done i/o 7 = data no yes read i/o 6 no yes i/o 6 toggle read i/o 6 51002-17
14 syncmos F29C51001t/F29C51001b F29C51001t/f 29c51001b v1.0 may 1999 package diagrams 32-pin plastic dip 32-pin plcc 15 ? max 0.545/0.555 index-1 .047 +.012 e 0 0.210 max 0.120 min 0.010 min .600 typ 1.660 max. .050 max .100 typ .032 +.012 e 0 .018 +.006 e .002 .010 +.004 e .0004 index-2 ejector mark .420 .003 3 ? - 6 ? 3 ? - 6 ? 3 ? - 6 ? .017 30 ? .136 .003 .110 .046 .003 .025 .050 typ .450 .003 .490 .005 .045x45 ? .590 .005 .550 .003 2 0 1 9 18 1 7 1 6 1 5 14 21 22 23 24 25 26 27 28 29 3 0 3 1 32 1 2 3 4 13 12 11 10 9 8 7 6 5
syncmos F29C51001t/F29C51001b 15 F29C51001t/f 29c51001b v1.0 may 1999 32-pin tsop-i 0.032 typ. 0.020 sbc 0.003 max 0.020 max. 0.024 0.004 seating plane 0.010 see detail a detail a 0.724 typ. (0.728 max.) 0.787 0.008 0.009 0.002 0.315 typ. (0.319 max.) 0.035 0.002 0.047 max. 0.005 min. 0.007 max. units in inches
syncmos t echnology inc. sa l e s o ff i c e : n o . 1, c r ea t i o n r d . 1 , s c i e n c e- b a s ed i n d u s t r i al pa r k , h s i n c h u , t a i w a n , r. o .c. t el : 886-3-5792926 fax : 886-3-5792953 n o t e 1 : p u b l i c a t i o n d a t e : may 1 9 9 9. r e v . a n o t e 2 : a l l d a t a a n d s p e c i f i c a t i o n a r e s u b j e c t t o c h a ng e w i t ho u t n o t i c e. F29C51001t/F29C51001b v1.0 may 1999 16

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